EVAL-AD1958EB【PDF 7/8 页】PLL/Multibit DAC

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AD1958

–7–

CLATCH

CCLK

CDATA

D15

D14

Figure 1. Format of SPI Signal

LRCLK

BCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

MSB

LSB

LEFT-JUSTIFIED MODE—16 TO 24 BITS PER CHANNEL

S MODE—16 TO 24 BITS PER CHANNEL

RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL

DSP MODE—16 TO 24 BITS PER CHANNEL

1/f

NOTES

1. DSP MODE DOES NOT IDENTIFY CHANNEL.

2. LRCLK NORMALLY OPERATES AT f

EXCEPT FOR DSP MODE WHICH IS 2

3. BCLK FREQUENCY IS NORMALLY 64

LRCLK BUT MAY BE OPERATED IN BURST MODE.

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

LSB

Figure 2. Stereo Serial Modes

The SPI control port is a 3-wire serial control port. The format

is similar to the Motorola SPI format except the input data word

is 16 bits wide. Max serial bit clock frequency is 8 MHz and

may be completely asynchronous to the PLL system or the

DAC. Figure 1 shows the format of the SPI signal. Note that

the CCLK can be gated or continuous,

CLATCH

should be

low during the 16 active clocks.

POWER SUPPLY AND VOLTAGE REFERENCE

The AD1958 is designed for five-volt supplies. Separate power

supply pins are provided for the analog, digital, and PLL sec-

tions.

These pins should be bypassed with 100 nF ceramic

chip capacitors, as close to the pins as possible, to minimize

noise. A bulk aluminum electrolytic capacitor of at least 22

should also be provided on the same PC board. For best perfor-

mance it is recommended that the analog supply be separate

from the digital and PLL supply. It is recommended that all

supplies be isolated by ferrite beads in series with each supply. It

is expected that the digital and PLL sections will be run from a

common supply but isolated from one another. It is important

that the analog supply be as clean as possible.

The internal voltage reference is brought out on Pin 21 (FILTR)

and should be bypassed as close as possible to the chip with a

parallel combination of 10

F and 100 nF. The reference volt-

age may be used to bias external op amps to the common-mode

voltage of the analog output signal pins. The current drawn

from the FILTR pin should be limited to less than 50

SERIAL DATA PORTS—DATA FORMAT

The DAC serial data input mode defaults to I

S. By changing

Bits 4 and 5 in the DAC control register, the mode can be

changed to RJ, DSP, or LJ. The word width defaults to 24 bits

but can be changed by programming Bits 8 and 9 in the DAC

Control Register.

Figure 2 shows the serial mode formats.

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